The present invention relates to a multi-processor system, and more particularly to a buffer control system suitable for use in a system having a cache or buffer memory in each processor.
A technique to provide a cache memory and a cache directory having a plurality of line entries corresponding to a plurality of line positions corresponding to line positions of the cache memory, in each processor of a multi-processor system and have each line entry hold an exclusive bit, a change bit and a validity bit is described in U.S. Pat. Nos. 4,394,731 and 4,400,770.
Each processor in the multi-processor system having a cache memory or buffer memory therein is provided with an exclusive bit in a buffer directory for determining whether it is necessary to cancel the content of the buffer in another processor during a write mode. As a result, the frequency of cancelling the buffer in the multi-processor system is reduced and a system performance is enhanced.
An effect of the exclusive bit is as follows. If a line in the buffer in each processor of the multi-processor system is not stored in the buffer of another processor, the exclusive bit is "1", and if there is a possibility that the line is stored in the buffer of another processor, the exclusive bit is "0". When data is to be written in the line, the exclusive bit is examined and only if the exclusive bit is "0", it is necessary to start buffer cancellation to the other processor. If the exclusive bit is "1", it is assured that a copy of that line is not stored in the buffer of the other processor and hence the processor does not start the buffer cancellation to the other processor.
When data is to be written into the line having the "0" exclusive bit, the buffer cancellation of the other processor is effected and after the assurance that there is no copy of the same line in the buffer of the other processor, the exclusive bit is set to "1".
However, the prior art system did not pay attention to detection of errors in the exclusive bit and the change bit which indicates a write status of the buffer and error recovery when the error is detected. In the prior art system, in order to detect the error in the exclusive bit or change bit, it is necessary to provide a parity bit for each of the exclusive bit and change bit or multiplex the exclusive bit and change bit. In order to recover the error, it is necessary to triplex the system and use a majority logic, or add error checking and correction code (ECC).
In the prior art system, a quantity of information to be held for the detection of error and the recovery of the error of the exclusive bit and change bit increases, and a theory for detecting and recovering the effect is complex.